SH7211 Datasheet, PDF (694/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.1 Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
15.3.2 Receive FIFO Data Register (SCFRDR)
SCFRDR is a register that stores serial receive data. The SCIF completes the reception of one byte
of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR
for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not
write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is
undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is initialized to an undefined value by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
Rev. 2.00 May. 08, 2008 Page 670 of 1200
REJ09B0344-0200