SH7211 Datasheet, PDF (753/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 16 I²C Bus Interface 3 (IIC3)
16.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I²C bus interface 3,
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
ICCR1 is initialized to H'00 by a power-on reset.
Bit: 7
6
5
ICE RCVD MST
Initial value: 0
0
0
R/W: R/W R/W R/W
4
TRS
0
R/W
3
0
R/W
2
1
CKS[3:0]
0
0
R/W R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface 3 Enable
0: This module is halted. (SCL and SDA pins function
as ports.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W Reception Disable
Enables or disables continuous reception when TRS =
0 and ICDRR is not read. If ICDRR cannot be read by
the rising of 8th clock cycle of SCL in master receive
mode, reception in byte units should be performed by
setting the RCVD bit to 1.
0: Enables continuous reception
1: Disables continuous reception
Rev. 2.00 May. 08, 2008 Page 729 of 1200
REJ09B0344-0200