SH7211 Datasheet, PDF (200/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
6. SRAM interface with byte selection
⎯ Can connect directly to a SRAM with byte selection.
7. Burst ROM interface (clock synchronous)
⎯ Can connect directly to a ROM of the clock-synchronous type.
8. Bus arbitration
⎯ Shares all of the resources with other CPU and outputs the bus enable after receiving the
bus request from external devices.
9. Refresh function
⎯ Supports the auto-refresh and self-refresh functions.
⎯ Specifies the refresh interval using the refresh counter and clock selection.
⎯ Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
10. Usage as interval timer for refresh counter
⎯ Generates an interrupt request at compare match.
Rev. 2.00 May. 08, 2008 Page 176 of 1200
REJ09B0344-0200