SH7211 Datasheet, PDF (165/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.9.1
Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC
Activating
1 Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating
sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC.
2. When interrupts occur, interrupt requests are sent to the CPU.
3. The CPU clears the interrupt source and performs the necessary processing in the interrupt
exception service routine.
6.9.2
Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU
Interrupt
1. Select DMAC activating sources and set both the DE and DME bits to 1. This masks CPU
interrupt sources regardless of the interrupt priority register settings.
2. Activating sources are applied to the DMAC when interrupts occur.
3. The DMAC clears the interrupt sources when starting transfer.
6.10 Usage Note
6.10.1 Timing to Clear an Interrupt Source
The interrupt source flags should be cleared in the interrupt exception service routine. After
clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt
controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal
to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually
cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently
accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE
instruction.
Rev. 2.00 May. 08, 2008 Page 141 of 1200
REJ09B0344-0200