SH7211 Datasheet, PDF (639/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
Initial
Bit Bit Name Value
12
POE0F
0
11 to 9 ⎯
All 0
8
PIE1
0
7, 6 POE3M[1:0] 00
R/W Description
R/(W)*¹ POE0 Flag
Indicates that a high impedance request has been input
to the POE0 pin.
[Clear conditions]
• By writing 0 to POE0F after reading POE0F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR1)
• By writing 0 to POE0F after reading POE0F = 1 after
a high level input to POE0 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR1)
[Set condition]
• When the input set by bits 1 and 0 in ICSR1 occurs at
the POE0 pin
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Port Interrupt Enable 1
Enables or disables interrupt requests when any one of
the POE0F, POE1F, and POE3F bits of the ICSR1 is set
to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
R/W*²
POE3 Mode
These bits select the input mode of the POE3 pin.
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE3 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE3 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Rev. 2.00 May. 08, 2008 Page 615 of 1200
REJ09B0344-0200