SH7211 Datasheet, PDF (712/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.3 SCSMR Settings
n
Clock Source
CKS1
0
Pφ
0
1
Pφ/4
0
2
Pφ/16
1
3
Pφ/64
1
SCSMR Settings
CKS0
0
1
0
1
The bit rate error in asynchronous is given by the following formula:
(1) In normal mode (when the ABCS bit in SCSEMR is 0)
Error (%) =
Pφ × 10⁶
− 1 × 100
(N + 1) × B × 64 × 2^2n-1
(2) In serial extended mode (when the ABCS bit in SCSEMR is 1)
Error (%) =
Pφ × 10⁶
− 1 × 100
(N + 1) × B × 32 × 2^2n-1
Table 15.4 lists examples of SCBRR settings in asynchronous mode, and table 15.5 lists examples
of SCBRR settings in clocked synchronous mode.
Rev. 2.00 May. 08, 2008 Page 688 of 1200
REJ09B0344-0200