SH7211 Datasheet, PDF (36/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 1 Overview
Classification Symbol
I/O
Bus control
DQMLL
O
DQMLU
O
RASL
O
CASL
O
CKE
O
REFOUT
O
Direct memory DREQ3 to
I
access controller DREQ0
(DMAC)
DACK3 to
O
DACK0
TEND1, TEND0 O
Multi-function TCLKA,
I
timer pulse unit TCLKB,
2 (MTU2)
TCLKC,
TCLKD
TIOC0A,
I/O
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
I/O
TIOC1B
TIOC2A,
I/O
TIOC2B
TIOC3A,
I/O
TIOC3B,
TIOC3C,
TIOC3D
Name
Function
Byte select
Selects bits D7 to D0 when SDRAM
is connected.
Byte select
RAS
CAS
Selects bits D15 to D8 when
SDRAM is connected.
Connected to the RAS pin when
SDRAM is connected.
Connected to the CAS pin when
SDRAM is connected.
CK enable
Connected to the CKE pin when
SDRAM is connected.
Refresh request Request signal for refresh execution.
DMA-transfer
request
Input pins to receive external
requests for DMA transfer.
DMA-transfer
request accept
Output pins for signals indicating
acceptance of external requests
from external devices.
DMA-transfer end Output pins for DMA transfer end.
output
MTU2 timer clock External clock input pins for the
input
timer.
MTU2 input
capture/output
compare
(channel 0)
MTU2 input
capture/output
compare
(channel 1)
MTU2 input
capture/output
compare
(channel 2)
MTU2 input
capture/output
compare
(channel 3)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins.
The TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins.
The TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins.
The TGRA_3 to TGRD_3 input
capture input/output compare
output/PWM output pins.
Rev. 2.00 May. 08, 2008 Page 12 of 1200
REJ09B0344-0200