SH7211 Datasheet, PDF (460/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.31 Timer Dead Time Enable Register (TDER)
TDER is an 8-bit readable/writable register that controls dead time generation in complementary
PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT
stops.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
- TDER
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R R/(W)
Initial
Bit
Bit Name Value R/W Description
7 to 1 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
TDER
1
R/(W) Dead Time Enable
Specifies whether to generate dead time.
0: Does not generate dead time
1: Generates dead time*
[Clearing condition]
• When 0 is written to TDER after reading TDER = 1
Note: * TDDR must be set to 1 or a larger value.
Rev. 2.00 May. 08, 2008 Page 436 of 1200
REJ09B0344-0200