SH7211 Datasheet, PDF (27/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 1 Overview
Items
ROM cache
Interrupt controller
(INTC)
Bus state controller
(BSC)
Specification
• Instruction/data separation system
• Instruction prefetch cache: Full/set associative
• Instruction prefetch miss cache: Full/set associative
• Data cache: Full/set associative
• Line size: 16 bytes
• Hardware prefetch function (continuous/branch prefetch)
• Nine external interrupt pins (NMI and IRQ7 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• 16 priority levels available
• Register bank enabling fast register saving and restoring in interrupt
processing
• Address space divided into eight areas (0 to 7), each a maximum of 64
Mbytes
• External bus: 8 or 16 bits
• The following features settable for each area independently
⎯ Supports both big endian and little endian for data access
⎯ Bus size (8 or 16 bits): Available sizes depend on the area.
⎯ Number of access wait cycles (different wait cycles can be
specified for read and write access cycles in some areas)
⎯ Idle wait cycle insertion (between same area access cycles or
different area access cycles)
⎯ Specifying the memory to be connected to each area enables
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface is also available.
⎯ Outputs a chip select signal (CS0 to CS7) according to the target
area (CS assert or negate timing can be selected by software)
• SDRAM refresh
Auto refresh or self refresh mode selectable
• SDRAM burst access
Rev. 2.00 May. 08, 2008 Page 3 of 1200
REJ09B0344-0200