SH7211 Datasheet, PDF (652/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
Initial
Bit
Bit Name
Value R/W Description
13
MTU2P2CZE 1
R/W* MTU2 Port 2 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PB4/TIOC4A and PB6/TIOC4C
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE3F, and
MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
12
MTU2P3CZE 1
R/W* MTU2 Port 3 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PB5/TIOC4B and PB7/TIOC4D
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE3F, and
MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
11
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
MTU2SP1CZE 1
R/W* MTU2S Port 1 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PB21/TIOC3BS and
PB20/TIOC3DS pins and to place them in high-
impedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE7F, and MTU2SHIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
Rev. 2.00 May. 08, 2008 Page 628 of 1200
REJ09B0344-0200