SH7211 Datasheet, PDF (654/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.4 Operation
Table 12.4 shows the target pins for high-impedance control and conditions to place the pins in
high-impedance state.
Table 12.4 Target Pins and Conditions for High-Impedance Control
Pins
Conditions
MTU2 high-current pins
(PB18/TIOC3B and
PB19/TIOC3D)
Input level detection,
output level comparison, or
SPOER setting
MTU2 high-current pins
(PB4/TIOC4A and
PB6/TIOC4C)
Input level detection,
output level comparison, or
SPOER setting
MTU2 high-current pins
(PB5/TIOC4B and
PB7/TIOC4D)
Input level detection,
output level comparison, or
SPOER setting
MTU2S high-current pins Input level detection,
(PB21/TIOC3BS and
output level comparison, or
PB20/TIOC3DS)
SPOER setting
MTU2S high-current pins Input level detection,
(PB12/TIOC4AS and
output level comparison, or
PB10/TIOC4CS)
SPOER setting
MTU2S high-current pins Input level detection,
(PB13/TIOC4BS and
output level comparison, or
PB11/TIOC4DS)
SPOER setting
MTU2 channel 0 pins
(PA22/TIOC0A,
PA23/TIOC0B,
PA24/TIOC0C, and
PA25/TIOC0D)
Input level detection or
SPOER setting
Detailed Conditions
MTU2P1CZE •
((POE3F+POE1F+POE0F) + (OSF1 •
OCE1) + (MTU2CH34HIZ))
MTU2P2CZE •
((POE3F+POE1F+POE0F) + (OSF1 •
OCE1) + (MTU2CH34HIZ))
MTU2P3CZE •
((POE3F+POE1F+POE0F) + (OSF1 •
OCE1) + (MTU2CH34HIZ))
MTU2SP1CZE •
((POE4F+POE7F) + (OSF2 • OCE2) +
(MTU2SHIZ))
MTU2SP2CZE •
((POE4F+POE7F) + (OSF2 • OCE2) +
(MTU2SHIZ))
MTU2SP3CZE •
((POE4F+POE7F) + (OSF2 • OCE2) +
(MTU2SHIZ))
((POE8F • POE8E) + (MTU2CH0HIZ))
Rev. 2.00 May. 08, 2008 Page 630 of 1200
REJ09B0344-0200