SH7211 Datasheet, PDF (262/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.5.4 CSn Assert Period Expansion
The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 8.9 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
Th
T1
T2
Tf
Read
Write
CK
A25 to A0
CSn
RD/WR
RD
D15 to D0
WEn
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.9 CSn Assert Period Expansion
Rev. 2.00 May. 08, 2008 Page 238 of 1200
REJ09B0344-0200