SH7211 Datasheet, PDF (11/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

5.5.1 Interrupt Sources..................................................................................................... 90
5.5.2 Interrupt Priority Level ........................................................................................... 91
5.5.3 Interrupt Exception Handling.................................................................................. 92
5.6 Exceptions Triggered by Instructions .................................................................................. 93
5.6.1 Types of Exceptions Triggered by Instructions ...................................................... 93
5.6.2 Trap Instructions ..................................................................................................... 94
5.6.3 Slot Illegal Instructions ........................................................................................... 94
5.6.4 General Illegal Instructions..................................................................................... 95
5.6.5 Integer Division Instructions................................................................................... 95
5.7 When Exception Sources Are Not Accepted ....................................................................... 96
5.8 Stack Status after Exception Handling Ends........................................................................ 97
5.9 Usage Notes ......................................................................................................................... 99
5.9.1 Value of Stack Pointer (SP) .................................................................................... 99
5.9.2 Value of Vector Base Register (VBR) .................................................................... 99
5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ........... 99
Section 6 Interrupt Controller (INTC) .................................................................101
6.1 Features.............................................................................................................................. 101
6.2 Input/Output Pins ............................................................................................................... 103
6.3 Register Descriptions ......................................................................................................... 104
6.3.1 Interrupt Priority Registers 01, 02, 05 to 15 (IPR01, IPR02, IPR05 to IPR15) .... 105
6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 107
6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 108
6.3.4 IRQ Interrupt Request Register (IRQRR)............................................................. 109
6.3.5 Bank Control Register (IBCR).............................................................................. 111
6.3.6 Bank Number Register (IBNR)............................................................................. 112
6.4 Interrupt Sources................................................................................................................ 114
6.4.1 NMI Interrupt........................................................................................................ 114
6.4.2 User Break Interrupt ............................................................................................. 114
6.4.3 H-UDI Interrupt .................................................................................................... 114
6.4.4 IRQ Interrupts ....................................................................................................... 115
6.4.5 On-Chip Peripheral Module Interrupts ................................................................. 116
6.5 Interrupt Exception Handling Vector Table and Priority ................................................... 117
6.6 Operation ........................................................................................................................... 125
6.6.1 Interrupt Operation Sequence ............................................................................... 125
6.6.2 Stack after Interrupt Exception Handling ............................................................. 128
6.7 Interrupt Response Time.................................................................................................... 129
6.8 Register Banks ................................................................................................................... 135
6.8.1 Banked Register and Input/Output of Banks ........................................................ 136
6.8.2 Bank Save and Restore Operations....................................................................... 136
Rev. 2.00 May. 08, 2008 Page xi of xxiv
REJ09B0344-0200