SH7211 Datasheet, PDF (752/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 16 I²C Bus Interface 3 (IIC3)
16.3 Register Descriptions
The I²C bus interface 3 has the following registers.
Table 16.2 Register Configuration
Register Name
Abbreviation R/W
I²C bus control register 1
ICCR1
R/W
I²C bus control register 2
ICCR2
R/W
I²C bus mode register
ICMR
R/W
I²C bus interrupt enable register ICIER
R/W
I²C bus status register
ICSR
R/W
Slave address register
SAR
R/W
I²C bus transmit data register ICDRT
R/W
I²C bus receive data register
ICDRR
R/W
NF2CYC register
NF2CYC
R/W
Initial
Value
H'00
H'7D
H'38
H'00
H'00
H'00
H'FF
H'FF
H'00
Address
H'FFFEE000
H'FFFEE001
H'FFFEE002
H'FFFEE003
H'FFFEE004
H'FFFEE005
H'FFFEE006
H'FFFEE007
H'FFFEE008
Access
Size
8
8
8
8
8
8
8
8
8
Rev. 2.00 May. 08, 2008 Page 728 of 1200
REJ09B0344-0200