SH7211 Datasheet, PDF (527/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
TGRA_3
TCDR
MTU2-MTU2S
synchronous clearing
Bit WRE = 1
Bit SCC = 1
TGRB_3
Counters
are not cleared
TCNT_3
(MTU2S)
TCNT_4
(MTU2S)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 10.64 Example of Synchronous Clearing in Dead Time during Up-Counting
(Timing (3) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)
Rev. 2.00 May. 08, 2008 Page 503 of 1200
REJ09B0344-0200