SH7211 Datasheet, PDF (258/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
CK
T1
T2
T1
T2
A25 to A0
CSn
RD/WR
Read
Write
RD
D15 to D0
WEn
D15 to D0
BS
DACKn ^*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 8.4 Continuous Access for Normal Space 2
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1
(Access Wait = 0, Cycle Wait = 0)
Rev. 2.00 May. 08, 2008 Page 234 of 1200
REJ09B0344-0200