SH7211 Datasheet, PDF (237/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Bit
6
5 to 2
1, 0
Bit Name
WM
⎯
HW[1:0]
Initial
Value
0
All 0
00
R/W Description
R/W External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address,
CS4 Negation
Specify the number of delay cycles from RD and WEn
negation to address and CS4 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 2.00 May. 08, 2008 Page 213 of 1200
REJ09B0344-0200