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SH7211 Datasheet, PDF (69/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family | |||
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Instruction
CLIPS.B Rn
CLIPS.W Rn
CLIPU.B Rn
CLIPU.W Rn
DIV1
Rm,Rn
DIV0S Rm,Rn
DIV0U
DIVS
R0,Rn
DIVU
R0,Rn
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
Section 2 CPU
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
0100nnnn10010001 When Rn > (H'0000007F),
1
â¯
Yes
(H'0000007F) â Rn, 1 â CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80) â Rn, 1 â CS
0100nnnn10010101 When Rn > (H'00007FFF), 1
â¯
Yes
(H'00007FFF) â Rn, 1 â CS
When Rn < (H'FFFF8000),
(H'FFFF8000) â Rn, 1 â CS
0100nnnn10000001 When Rn > (H'000000FF), 1
â¯
Yes
(H'000000FF) â Rn, 1 â CS
0100nnnn10000101 When Rn > (H'0000FFFF), 1
â¯
Yes
(H'0000FFFF) â Rn, 1 â CS
0011nnnnmmmm0100 1-step division (Rn ÷ Rm)
1
Calcu- Yes Yes Yes
lation
result
0010nnnnmmmm0111 MSB of Rn â Q,
1
MSB of Rm â M, M ^ Q â T
Calcu- Yes Yes Yes
lation
result
0000000000011001 0 â M/Q/T
1
0
Yes Yes Yes
0100nnnn10010100 Signed operation of Rn ÷ R0 36
â¯
Yes
â Rn 32 ÷ 32 â 32 bits
0100nnnn10000100 Unsigned operation of Rn ÷ R0 34
â¯
Yes
â Rn 32 ÷ 32 â 32 bits
0011nnnnmmmm1101 Signed operation of Rn à Rm 2
â MACH, MACL
32 Ã 32 â 64 bits
â¯
Yes Yes Yes
0011nnnnmmmm0101 Unsigned operation of Rn à 2
Rm â MACH, MACL
32 Ã 32 â 64 bits
â¯
Yes Yes Yes
0100nnnn00010000 Rn â 1 â Rn
1
When Rn is 0, 1 â T
When Rn is not 0, 0 â T
Compa- Yes Yes Yes
rison
result
0110nnnnmmmm1110 Byte in Rm is
sign-extended â Rn
1
â¯
Yes Yes Yes
0110nnnnmmmm1111 Word in Rm is
sign-extended â Rn
1
â¯
Yes Yes Yes
Rev. 2.00 May. 08, 2008 Page 45 of 1200
REJ09B0344-0200
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