SH7211 Datasheet, PDF (338/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
Bit
15,14
Bit Name
DM[1:0]
13, 12 SM[1:0]
Initial
Value R/W Descriptions
00
R/W Destination Address Mode
These bits select whether the DMA destination
address is incremented, decremented, or left fixed. (In
single address mode, DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (Setting prohibited in 16-
byte transfer)
01: Destination address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit transfer,
+16 in 16-byte transfer)
10: Destination address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer,
setting prohibited in 16-byte transfer)
11: Setting prohibited
00
R/W Source Address Mode
These bits select whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with
DACK.)
00: Fixed source address (Setting prohibited in 16-
byte-unit transfer)
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte-unit transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer, setting prohibited in 16-byte-unit
transfer)
11: Setting prohibited
Rev. 2.00 May. 08, 2008 Page 314 of 1200
REJ09B0344-0200