SH7211 Datasheet, PDF (950/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
(2) Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 21.11.
Start programming
procedure program
Set internal clock ratio by
frequency control register
(FRQCR) to 4: 4: 4
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(2.1)
Set FKEY to H'A5
After clearing VBR,
set SCO to 1 and
execute download
(2.2)
(2.3)
Clear FKEY to 0
(2.4)
DPFR=0?
Yes
(2.5)
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
(2.6)
Initialization
JSR FTDAR setting+32 (2.7)
FPFR=0?
Yes
1
(2.8)
No
Initialization error processing
1
Set FKEY to H'5A
(2.9)
Set parameter to R4 and
R5 (FMPAR and FMPDR)
(2.10)
Programming
JSR FTDAR setting+16
(2.11)
FPFR=0?
(2.12)
No
Yes
Clear FKEY and
programming
error processing
No
Required data
programming is
completed?
(2.13)
Yes
Clear FKEY to 0
(2.14)
End programming
procedure program
Figure 21.11 Programming Procedure
The details of the programming procedure are described below. The procedure program must be
executed in an area other than the flash memory to be programmed. Especially the part where the
SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify 4:4:4
as the frequency division ratios of an internal clock (Iφ), a bus clock (Bφ), and a peripheral clock
(Pφ) through the frequency control register (FRQCR).
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 21.8.2, Areas for Storage of the Procedural Program
and Data for Programming.
Rev. 2.00 May. 08, 2008 Page 926 of 1200
REJ09B0344-0200