SH7211 Datasheet, PDF (115/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
5.5.2 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts processing
according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels
of IRQ interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt
priority registers 01, 02, and 05 to 15 (IPR01, IPR02, and IPR05 to IPR15) of the INTC as shown
in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section
6.3.1, Interrupt Priority Registers 01, 02, 05 to 15 (IPR01, IPR02, IPR05 to IPR15), for details of
IPR01, IPR02, and IPR05 to IPR15.
Table 5.8 Interrupt Priority Order
Type
Priority Level
NMI
16
User break
15
H-UDI
15
IRQ
0 to 15
On-chip peripheral module
Comment
Fixed priority level. Cannot be masked.
Fixed priority level.
Fixed priority level.
Set with interrupt priority registers 01, 02, and 05
to 15 (IPR01, IPR02, and IPR05 to IPR15).
Rev. 2.00 May. 08, 2008 Page 91 of 1200
REJ09B0344-0200