SH7211 Datasheet, PDF (1177/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
9.3.4 DMA Channel
Control Registers
(CHCR)
Page
313
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name Value R/W Descriptions
16
AL
0
R/W Acknowledge Level
Specifies the DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK
9.3.5 DMA Reload
318
Source Address
Registers (RSAR)
9.3.6 DMA Reload
319
Destination Address
Registers (RDAR)
9.3.7 DMA Reload
320
Transfer Count Registers
(RDMATCR)
10.1 Features
353
Table 10.1 MTU2
Functions
Figure amended
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Figure amended
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Figure amended
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table amended
Item
DMAC activation
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
TGR
TGR
TGR
TGR
TGR
—
compare
compare
compare
compare
compare
match or
match or
match or
match or
match or
input capture input capture input capture input capture input capture
Rev. 2.00 May. 08, 2008 Page 1153 of 1200
REJ09B0344-0200