SH7211 Datasheet, PDF (1213/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
27.4.1 Clock Timing −
Figure 27.3 CKL Clock
Input Timing
27.4.2 Control Signal 1093
Timing
Table 27.7 Control
Signal Timing
27.4.3 Bus Timing
1096
Table 27.8 Bus Timing
1097
27.4.4 UBC Trigger
Timing
1126
Table 27.9 UBC Trigger
Timing
27.4.5 DMAC Module 1126
Timing
Table 27.10 DMAC
Module Timing
27.4.6 MTU2, MTU2S 1128
Module Timing
Table 27.11 MTU2,
MTU2S Module Timing
Revision (See Manual for Details)
Figure deleted
Conditions amended
Conditions: V_CC = PLLV_CC = 1.4 V to 1.6 V, V_CCQ = 3.0 V to
3.6 V, V_SS = PLLV_SS = V_SSQ = 0 V, Ta = −40°C to +85°C
Table amended
Item
MD1, MD0 setup time
Symbol
tMDS
Bφ = 40 MHz
Min.
Max.
20
−
Unit
tcyc
Notes amended
Notes: 2. In standby mode or when the clock multiplication
ratio is changed, t_RESW = t_OSC2 (Min. 10 ms).
3. In standby mode, t_RESW = t_OSC2 (Min. 10 ms).
Conditions amended
Conditions: Clock mode 6, V_CC = PLLV_CC = 1.4 V to 1.6 V, V_CCQ
= 3.0 V to 3.6 V, V_SS = PLLV_SS = V_SSQ = 0 V, Ta = −40°C to
+85°C
Table amended
Item
Read data hold time 2
Symbol
tRDH2
Bφ = 40 MHz*
Min.
Max.
2
−
Conditions amended
Conditions: V_CC = PLLV_CC = 1.4 to 1.6 V, V_CCQ = 3.0 to 3.6 V,
V_SS = PLLV_SS = V_SSQ = 0 V, Ta = −40°C to +85°C
Conditions amended
Conditions: V_CC = PLLV_CC = 1.4 to 1.6 V, V_CCQ = 3.0 to 3.6 V,
V_SS = PLLV_SS = V_SSQ = 0 V, Ta = −40°C to +85°C
Conditions amended
Conditions: V_CC = PLLV_CC = 1.4 to 1.6 V, V_CCQ = 3.0 to 3.6 V,
V_SS = PLLV_SS = V_SSQ = 0 V, Ta = −40°C to +85°C
Rev. 2.00 May. 08, 2008 Page 1189 of 1200
REJ09B0344-0200