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SH7211 Datasheet, PDF (452/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name value R/W Description
5
N
0
R/W Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
4
P
0
R/W Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
3
FB*
0
R/W External Feedback Signal Enable
This bit selects whether the switching of the output of
the positive/reverse phase is carried out automatically
with the MTU2/channel 0 TGRA, TGRB, TGRC input
capture signals or by writing 0 or 1 to bits 2 to 0 in
TGCR.
0: Output switching is external input (Input sources are
channel 0 TGRA, TGRB, TGRC input capture signal)
1: Output switching is carried out by software (setting
values of UF, VF, and WF in TGCR).
2
WF
1
VF
0
UF
0
R/W Output Phase Switch 2 to 0
0
R/W These bits set the positive phase/negative phase output
0
R/W phase on or off state. The setting of these bits is valid
only when the FB bit in this register is set to 1. In this
case, the setting of bits 2 to 0 is a substitute for external
input. See table 10.39.
Note: * If the BDC bit in the MTU2S is set to 1, the FB bit should not be cleared to 0.
Rev. 2.00 May. 08, 2008 Page 428 of 1200
REJ09B0344-0200