SH7211 Datasheet, PDF (65/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
Instruction
Instruction Code
Operation
MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn)
MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn)
MOV.B @(R0,Rm),Rn
0000nnnnmmmm1100 (R0 + Rm) →
sign extension → Rn
MOV.W @(R0,Rm),Rn
0000nnnnmmmm1101 (R0 + Rm) →
sign extension → Rn
MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn
MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR)
MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR)
MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR)
MOV.B
@(disp,GBR),R0 11000100dddddddd (disp + GBR) →
sign extension → R0
MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) →
sign extension → R0
MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0
MOV.B R0,@Rn+
0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn
MOV.W R0,@Rn+
0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn
MOV.L R0,@Rn+
0100nnnn10101011 R0 → Rn), Rn + 4 → Rn
MOV.B @-Rm,R0
0100mmmm11001011 Rm-1 → Rm, (Rm) →
sign extension → R0
MOV.W @-Rm,R0
0100mmmm11011011 Rm-2 → Rm, (Rm) →
sign extension → R0
MOV.L @-Rm,R0
0100mmmm11101011 Rm-4 → Rm, (Rm) → R0
MOV.B Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp + Rn)
0000dddddddddddd
MOV.W Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp × 2 + Rn)
0001dddddddddddd
MOV.L Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp × 4 + Rn)
0010dddddddddddd
MOV.B
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) →
sign extension → Rn
0100dddddddddddd
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯ Yes Yes Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
Rev. 2.00 May. 08, 2008 Page 41 of 1200
REJ09B0344-0200