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| SH7211 Datasheet, PDF (277/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family | |||
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Section 8 Bus State Controller (BSC)
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Tw
Td1
Td2
Td3
Td4
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tde (Tap)
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.15 Burst Read Wait Specification Timing (CAS Latency 2,
WTRCD[1:0] = 1 Cycle, Auto-Precharge)
Rev. 2.00 May. 08, 2008 Page 253 of 1200
REJ09B0344-0200
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