SH7211 Datasheet, PDF (902/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 20 I/O Ports
20.3.2 Port D Data Register L (PDDRL)
PDDRL is a 16-bit readable/writable register that stores port D data. Bits PD15DR to PD0DR
correspond to pins PD15 to PD0, respectively.
When a pin function is general output, if a value is written to PDDRL, the value is output directly
from the pin, and if PDDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PDDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PDDRL, although that value is written into PDDRL, it
does not affect the pin state. Table 20.8 summarizes PDDRL read/write operations.
PDDRL is initialized to the respective values shown in table 20.5 by a power-on reset, but is not
initialized by a manual reset or in sleep mode or software standby mode.
Bit:
Initial value:
R/W:
15
PD15
DR
0
R/W
14
PD14
DR
0
R/W
13
PD13
DR
0
R/W
12
PD12
DR
0
R/W
11
PD11
DR
0
R/W
10
PD10
DR
0
R/W
9
PD9
DR
0
R/W
8
PD8
DR
0
R/W
7
PD7
DR
0
R/W
6
PD6
DR
0
R/W
5
PD5
DR
0
R/W
4
PD4
DR
0
R/W
3
PD3
DR
0
R/W
2
PD2
DR
0
R/W
1
PD1
DR
0
R/W
0
PD0
DR
0
R/W
Rev. 2.00 May. 08, 2008 Page 878 of 1200
REJ09B0344-0200