SH7211 Datasheet, PDF (1143/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
CSn
RD/WR
Tnop
Tc1
Tc2
Tc3
Tc4
t_AD1
t_CSD1
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
WRIT command
t_AD1
t_AD1
t_CSD1
t_RWD1
t_RWD1
t_RWD1
RASL
CASL
DQMLx
D15 to D0
BS
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 27.32 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
TRWL = 0 Cycle)
Rev. 2.00 May. 08, 2008 Page 1119 of 1200
REJ09B0344-0200