SH7211 Datasheet, PDF (1149/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

CK
A25 to A0
A12/A11^*1
CSn
RD/WR
RASL
CASL
DQMLx
D15 to D0
Tp
Tpw
Trr
t_AD3
t_AD3
t_AD3
t_AD3
t_CSD2
t_CSD2
t_CSD2
t_CSD2
t_RWD2
t_RWD2
t_RASD2
t_RASD2
t_RASD2
t_RASD2
t_CASD2
t_CASD2
t_CASD2
t_DQMD2
(Hi-Z)
Section 27 Electrical Characteristics
Trc
Trc
Trc
BS
CKE
DACKn
TENDn ^*2
t_CKED2
t_CKED2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 27.38 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
(WTRP = 2 Cycles)
Rev. 2.00 May. 08, 2008 Page 1125 of 1200
REJ09B0344-0200