SH7211 Datasheet, PDF (352/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR,
DMAOR, DMARS)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (one transfer unit);
DMATCR – 1 → DMATCR,
SAR and DAR updated
*²
Bus mode,
transfer request mode,
*³
DREQ detection system
No
DMATCR = 0?
Yes
TE = 1
DEI interrupt request
(when IE = 1)
When reload function is enabled,
RSAR → SAR, RDAR → DAR,
and RDMATCR → DMATCR
For a request from an
on-chip peripheral module,
the transfer acknowledge signal
is sent to the module.
No
DMATCR=1/2 ?
Yes
HE=1
HEI interrupt request
(when HE = 1)
When the TC bit in CHCR is 0, or
for a request from an on-chip peripheral
module, the transfer acknowledge
signal is sent to the module.
NMIF = 1
or AE = 1 or DE = 0
No
or DME = 0?
Yes
NMIF = 1
or AE = 1 or DE = 0
No
or DME = 0?
Yes
Transfer end
Normal end
Transfer terminated
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the
DE and DME bits are set to 1.
2. DREQ level detection in burst mode (external request) or cycle steal mode.
3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode.
Figure 9.2 DMA Transfer Flowchart
Rev. 2.00 May. 08, 2008 Page 328 of 1200
REJ09B0344-0200