SH7211 Datasheet, PDF (1131/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Tr
Tc1
Tcw
t_AD1
t_AD1
Row address
Column address
t_AD1
t_AD1
t_AD1
READA command
Td1
Tde
t_AD1
CSn
RD/WR
RASL
CASL
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_DQMD1
D15 to D0
BS
t_BSD
t_BSD
t_CSD1
t_RWD1
t_DQMD1
t_RDS2
tRDH2
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 27.20 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Rev. 2.00 May. 08, 2008 Page 1107 of 1200
REJ09B0344-0200