SH7211 Datasheet, PDF (141/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.5 Interrupt Exception Handling Vector Table and Priority
Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and
interrupt priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and vector table address offsets. In
interrupt exception handling, the interrupt exception service routine start address is fetched from
the vector table indicated by the vector table address. For details of calculation of the vector table
address, see table 5.4 in section 5, Exception Handling.
The priorities of IRQ interrupts and on-chip peripheral module interrupts can be set freely between
0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 15 (IPR01,
IPR02, and IPR05 to IPR15). However, if two or more interrupts specified by the same IPR
among IPR05 to IPR15 occur, the priorities are defined as shown in the IPR setting unit internal
priority of table 6.4, and the priorities cannot be changed. A power-on reset assigns priority level 0
to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to
two or more interrupt sources and interrupts from those sources occur simultaneously, they are
processed by the default priorities indicated in table 6.4.
Rev. 2.00 May. 08, 2008 Page 117 of 1200
REJ09B0344-0200