SH7211 Datasheet, PDF (921/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
Table 21.5 Register/Parameter and Target Mode
Initiali- Program-
RAM
Download zation ming
Erasure Read Emulation
Programming/ FCCS
√
erasing interface _FPCS
√
registers
FECS
√
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FKEY
√
—
√
√
—
—
FMATS —
—
√*¹
√*¹
√*²
—
FTDAR √
—
—
—
—
—
Programming/ DPFR
√
erasing interface _FPFR
—
parameters
FPEFEQ —
—
—
√
√
√
—
—
—
—
√
—
—
—
—
—
FUBRA —
√
—
—
—
—
FMPAR —
—
√
—
—
—
FMPDR —
—
√
—
—
—
FEBS
—
—
—
√
—
—
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
Rev. 2.00 May. 08, 2008 Page 897 of 1200
REJ09B0344-0200