SH7211 Datasheet, PDF (315/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Table 8.19 Number of Idle Cycles Inserted between Access Cycles to Different Memory
Types
Next Cycle
Burst ROM
MPX- Byte SRAM Byte SRAM
Previous Cycle SRAM (Asynchronous) I/O (BAS = 0) (BAS = 1) SDRAM
SDRAM
(Low-Frequency Burst ROM
Mode)
(Synchronous)
SRAM
0
0
1
0
1
1
1.5
0
Burst ROM
0
0
(asynchronous)
1
0
1
1
1.5
0
MPX-I/O
1
1
0
1
1
1
1.5
1
Byte SRAM
0
0
(BAS = 0)
1
0
1
1
1.5
0
Byte SRAM
1
1
(BAS = 1)
2
1
0
0
1.5
1
SDRAM
1
1
2
1
0
0
⎯
1
SDRAM
1.5
1.5
2.5 1.5
0.5
⎯
1
1.5
(low-frequency
mode)
Burst ROM
0
0
(synchronous)
1
0
1
1
1.5
0
Figure 8.39 shows sample estimation of idle cycles between access cycles. In the actual operation,
the idle cycles may become shorter than the estimated value due to the write buffer effect or may
become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU
instruction execution or CPU register conflicts. Please consider these errors when estimating the
idle cycles.
Rev. 2.00 May. 08, 2008 Page 291 of 1200
REJ09B0344-0200