SH7211 Datasheet, PDF (61/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
Operation
Classification Types Code
Function
No. of
Instructions
Logic
6
AND
Logical AND
14
operations
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit set
TST
Logical AND and T bit set
XOR
Exclusive OR
Shift
12
ROTL
One-bit left rotation
16
ROTR
One-bit right rotation
ROTCL One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAD
Dynamic arithmetic shift
SHAL
One-bit arithmetic left shift
SHAR
One-bit arithmetic right shift
SHLD
Dynamic logical shift
SHLL
One-bit logical left shift
SHLLn n-bit logical left shift
SHLR
One-bit logical right shift
SHLRn n-bit logical right shift
Branch
10
BF
Conditional branch, conditional delayed branch 15
(branch when T = 0)
BT
Conditional branch, conditional delayed branch
(branch when T = 1)
BRA
Unconditional delayed branch
BRAF
Unconditional delayed branch
BSR
Delayed branch to subroutine procedure
BSRF
Delayed branch to subroutine procedure
JMP
Unconditional delayed branch
JSR
Branch to subroutine procedure
Delayed branch to subroutine procedure
RTS
Return from subroutine procedure
Delayed return from subroutine procedure
RTV/N
Return from subroutine procedure with Rm →
R0 transfer
Rev. 2.00 May. 08, 2008 Page 37 of 1200
REJ09B0344-0200