SH7211 Datasheet, PDF (67/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
MOVRT Rn
0000nnnn00111001 ~T → Rn
1
⎯
Yes
MOVT Rn
0000nnnn00101001 T → Rn
1
⎯ Yes Yes Yes
MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) →
1
⎯
Yes
zero extension → Rn
1000dddddddddddd
MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp × 2 + Rm) →
1
⎯
Yes
zero extension → Rn
1001dddddddddddd
NOTT
0000000001101000 ~T → T
1
Ope-
Yes
ration
result
PREF @Rn
0000nnnn10000011 (Rn) → operand cache
1
⎯
Yes Yes
SWAP.B Rm,Rn
0110nnnnmmmm1000 Rm → swap lower 2 bytes → 1
Rn
⎯ Yes Yes Yes
SWAP.W Rm,Rn
0110nnnnmmmm1001 Rm → swap upper and lower 1
words → Rn
⎯ Yes Yes Yes
XTRCT Rm,Rn
0010nnnnmmmm1101 Middle 32 bits of Rm:Rn → Rn 1
⎯ Yes Yes Yes
Rev. 2.00 May. 08, 2008 Page 43 of 1200
REJ09B0344-0200