SH7211 Datasheet, PDF (1030/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 23 Power-Down Modes
The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely
reflected in the SLEEP instruction.
Table 23.4 Register States in Software Standby Mode
Module Name
Interrupt controller (INTC)
Clock pulse generator (CPG)
User break controller (UBC)
Bus state controller (BSC)
A/D converter (ADC)
I/O port
User debugging interface (H-UDI)
Serial communication interface with FIFO
(SCIF)
Direct memory access controller (DMAC)
Multi-function timer pulse unit 2 (MTU2)
Multi-function timer pulse unit 2S (MTU2S)
Port output enable 2 (POE2)
Compare match timer (CMT)
I²C bus interface 3 (IIC3)
D/A converter (DAC)
Registers Whose
Initialized Registers Content is Retained
⎯
All registers
⎯
All registers
⎯
All registers
⎯
All registers
All registers
⎯
⎯
All registers
⎯
All registers
⎯
All registers
⎯
⎯
⎯
⎯
All registers
BC2 and BC0 bits in
ICMR register
⎯
All registers
All registers
All registers
All registers
⎯
Other than BC[2:0] bits in
ICMR
All registers
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
values to secure the specified oscillation settling time.
3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction.
Rev. 2.00 May. 08, 2008 Page 1006 of 1200
REJ09B0344-0200