SH7211 Datasheet, PDF (540/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Skipping counter 3ACNT 0
1
2
3
0
1
2
3
0
Skipping counter 4VCNT
0
Buffer transfer-enabled period
(T3AEN is set to 1)
Buffer transfer-enabled period
(T4VEN is set to 1)
Buffer transfer-enabled period
(T3AEN and T4VEN are set to 1)
1
2
3
0
1
2
3
Note: MD[3:0] in TMDR_3 = 1111
Buffer transfer at the crest and trough is selected.
The skipping count is set to three.
T3AEN and T4VEN are set to 1.
Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer
Transfer-Enabled Period
Rev. 2.00 May. 08, 2008 Page 516 of 1200
REJ09B0344-0200