SH7211 Datasheet, PDF (122/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
Exception Type
General illegal instruction
Integer division instruction
Stack Status
SP
Start address of general
illegal instruction
SR
32 bits
32 bits
SP
Start address of relevant
integer division instruction
SR
32 bits
32 bits
Rev. 2.00 May. 08, 2008 Page 98 of 1200
REJ09B0344-0200