SH7211 Datasheet, PDF (211/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Bit
Bit Name
30 to 28 IWW[2:0]
Initial
Value
011
27 to 25 IWRWD[2:0] 011
R/W Description
R/W Idle Cycles between Write-Read Cycles and Write-
Write Cycles
These bits specify the number of idle cycles to be
inserted after the access to a memory that is
connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R/W Idle Cycles for Another Space Read-Write
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target access cycle is a read-write one in
which continuous access cycles switch between
different spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev. 2.00 May. 08, 2008 Page 187 of 1200
REJ09B0344-0200