SH7211 Datasheet, PDF (283/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
When bank active mode is set, if only access cycles to the respective banks in the area 3 space are
considered, as long as access cycles to the same row address continue, the operation starts with the
cycle in figure 8.19 or 8.23, followed by repetition of the cycle in figure 8.20 or 8.23. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 8.20 or 8.23 is executed instead of
that in figure 8.21 or 8.24. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
CK
A25 to A0
A12/A11*¹
CS3
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.19 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)
Rev. 2.00 May. 08, 2008 Page 259 of 1200
REJ09B0344-0200