SH7211 Datasheet, PDF (177/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Bit
Bit Name
7, 6 CD1[1:0]
5, 4 ID1[1:0]
3, 2 RW1[1:0]
1, 0 SZ1[1:0]
[Legend]
x: Don't care
Section 7 User Break Controller (UBC)
Initial
Value
00
00
00
00
R/W Description
R/W C Bus Cycle/I Bus Cycle Select 1
Select the C bus cycle or I bus cycle as the bus cycle
of the channel-1 break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
R/W Instruction Fetch/Data Access Select 1
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel-1 break condition. If
the instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
data access cycle
R/W Read/Write Select 1
Select the read cycle or write cycle as the bus cycle of
the channel-1 break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
R/W Operand Size Select 1
Select the operand size of the bus cycle for the
channel-1 break condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
Rev. 2.00 May. 08, 2008 Page 153 of 1200
REJ09B0344-0200