SH7211 Datasheet, PDF (637/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.3.1 Input Level Control/Status Register 1 (ICSR1)
ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1, and POE3 pin input
modes, controls the enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
POE3F - POE1F POE0F -
-
-
PIE1 POE3M[1:0]
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
R/W: R/(W)*¹ R R/(W)*¹ R/(W)*¹ R
R
R R/W R/W*² R/W*² R
4
3
2
1
0
-
POE1M[1:0] POE0M[1:0]
0
0
0
0
0
R R/W*² R/W*² R/W*² R/W*²
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Initial
Bit Bit Name Value R/W Description
15
POE3F 0
R/(W)*¹ POE3 Flag
Indicates that a high impedance request has been input
to the POE3 pin.
[Clearing conditions]
• By writing 0 to POE3F after reading POE3F = 1
(when the falling edge is selected by bits 7 and 6 in
ICSR1)
• By writing 0 to POE3F after reading POE3F = 1 after
a high level input to POE3 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 7 and 6 in ICSR1)
[Setting condition]
• When the input set by bits 7 and 6 in ICSR1 occurs at
the POE3 pin
Rev. 2.00 May. 08, 2008 Page 613 of 1200
REJ09B0344-0200