SH7211 Datasheet, PDF (534/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
TGCR
UF bit
VF bit
WF bit
6-phase output TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 1, P = 1, FB = 1, output active level = high
Figure 10.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)
(r) A/D Converter Start Request Setting
In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3
compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels
3 and 4.
When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started
at the crest of the TCNT_3 count.
A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable
register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the
TTGE2 bit in TIER_4 to 1.
Rev. 2.00 May. 08, 2008 Page 510 of 1200
REJ09B0344-0200