SH7211 Datasheet, PDF (373/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
9.5 Usage Note
9.5.1 Half-End Flag Setting and Half-End Interrupt
When monitoring the half-end flag status in CHCR or using the half-end interrupt together with
the reload function, the following precautions must be observed.
For the reload transfer count in RDMATCR, always set a value equal to the initial transfer count
(the value in DMATCR).
If the first setting of DMATCR differs from the RDMATCR setting used in the second and
following DMA transfer, the half-end flag setting timing may be earlier than half of the transfer
count or the half-end flag may not be set. The same is true for the half-end interrupt.
Rev. 2.00 May. 08, 2008 Page 349 of 1200
REJ09B0344-0200