SH7211 Datasheet, PDF (346/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
Bit
9, 8
7 to 3
2
1
Bit Name
PR[1:0]
⎯
AE
NMIF
Initial
Value
00
All 0
0
0
R/W Description
R/W Priority Mode
These bits select the priority level between channels
when there are transfer requests for multiple channels
simultaneously.
00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 >
CH5 > CH6 > CH7
01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 >
CH6 > CH3 > CH7
10: Setting prohibited
11: Round-robin mode (only supported in CH0 to CH3)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/(W)* Address Error Flag
Indicates whether an address error has occurred by
the DMAC. When this bit is set, even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1, DMA
transfer is not enabled. This bit can only be cleared by
writing 0 after reading 1.
0: No DMAC address error
1: DMAC address error occurred
[Clearing condition]
• Writing 0 after reading AE = 1
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. When this bit
is set, even if the DE bit in CHCR and the DME bit in
DMAOR are set to 1, DMA transfer is not enabled. This
bit can only be cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress
can be done in one transfer unit. Even if the NMI
interrupt is input while the DMAC is not in operation,
the NMIF bit is set to 1.
0: No NMI interrupt
1: NMI interrupt occurred
[Clearing condition]
• Writing 0 after reading NMIF = 1
Rev. 2.00 May. 08, 2008 Page 322 of 1200
REJ09B0344-0200