SH7211 Datasheet, PDF (539/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) When the buffer register is modified within one carrier cycle after a TGIA_3 interrupt has occurred
A TGIA_3 interrupt has occurred
A TGIA_3 interrupt has occurred
TCNT_3
TCNT_4
Buffer transfer-enabled period
TITCR[6:4]
TITCNT[6:4]
Buffer register
Temporary register
General register
Buffer register modification timing
Buffer register modification timing
0
Data
Data
Data
2
1
2
0
Data1
Data1
Data1
1
Data2
Data2
Data2
(2) When the buffer register is modified after one carrier cycle has been passed from a TGIA_3 interrupt occurrence
A TGIA_3 interrupt has occurred
A TGIA_3 interrupt has occurred
TCNT_3
TCNT_4
Buffer transfer-enabled period
TITCR[6:4]
TITCNT[6:4]
Buffer register
Buffer register modification timing
0
Data
2
1
2
0
1
Data1
Temporary register
Data
Data1
General register
Data
Data1
Note: MD[3:0] in TMDR_3 = 1101
Buffer transfer at the crest is selected.
The skipping count is set to two.
T3AEN and T4VEN are set to 1 and cleared to 0, respectively.
Figure 10.77 Example of Operation when Buffer Transfer is Linked with Interrupt
Skipping (BTE1 = 1 and BTE0 = 0)
Rev. 2.00 May. 08, 2008 Page 515 of 1200
REJ09B0344-0200