SH7211 Datasheet, PDF (93/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Bit
12
11, 10
9, 8
7
Bit Name
CKOEN
⎯
STC[1:0]
⎯
Initial
Value
1
All 0
00
0
R/W
R/W
R
R/W
R
Description
Clock Output Enable
Specifies whether a clock is output on the CK pin, or
the CK pin is placed in the level-fixed state during
software standby mode or when exiting software
standby mode.
If this bit is cleared to 0, the CK pin is fixed to the low
level during software standby mode or when exiting
software standby mode. Therefore, the malfunction of
an external circuit because of an unstable CK clock
upon exit from software standby mode can be
prevented.
0: The CK pin is fixed to the low level during software
standby mode or when exiting software standby
mode.
1: Clock is output from the CK pin (placed in the high-
impedance state during software standby mode).
Reserved
These bits are always read as 0. The write value
should always be 0.
Frequency multiplication ratio of PLL circuit 1
00: × 1 time
01: × 2 times
10: Setting prohibited
11: × 4 times
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 May. 08, 2008 Page 69 of 1200
REJ09B0344-0200