SH7211 Datasheet, PDF (1027/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 23 Power-Down Modes
23.3.6 System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM.
SYSCR2 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is valid.
When an RAMWE bit is set to 1, the corresponding on-chip RAM area is enabled. When an
RAMWE bit is cleared to 0, the corresponding on-chip RAM area cannot be written to. In this
case, writing to the on-chip RAM is ignored. The initial value of an RAMWE bit is 1.
Note that when clearing the RAMWE bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAMWE bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
located immediately after the instruction to write to SYSCR2. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
To enable the on-chip RAM by setting the RAMWE bit to 1, locate an instruction to read data
from SYSCR2 immediately after an instruction to write to SYSCR2. If an instruction to access the
on-chip RAM is located immediately after the instruction to write to SYSCR2, normal access is
not guaranteed.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
RAM RAM RAM RAM
WE3 WE2 WE1 WE0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R R/W R/W R/W R/W
Bit
7 to 4
3
Bit Name
⎯
Initial
Value
All 1
RAMWE3 1
R/W Description
R
Reserved
These bits are always read as 1. The write value
should always be 1.
R/W RAM Write Enable 3 (corresponding RAM addresses:
H'FFF86000 to H'FFF87FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
Rev. 2.00 May. 08, 2008 Page 1003 of 1200
REJ09B0344-0200