SH7211 Datasheet, PDF (801/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
17.3.3 A/D Start Trigger Select Register (ADSTRGR)
ADSTRGR selects an A/D conversion start trigger from the MTU2 or MTU2S. The A/D
conversion start trigger is used as an A/D conversion start source when the TRGE bit in ADCR is
set to 1 and the EXTRG bit in ADCR is set to 0.
Bit: 7
-
Initial value: 0
R/W: R
6
5
4
3
2
1
0
STR6 STR5 STR4 STR3 STR2 STR1 STR0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value R/W
7
⎯
0
R
6
STR6
0
R/W
5
STR5
0
R/W
4
STR4
0
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Start Trigger 6
Enables or disables the A/D conversion start request
input from the MTU2S.
0: Disables the A/D conversion start by TRGAN trigger
(MTU2S).
1: Enables the A/D conversion start by TRGAN trigger
(MTU2S).
Start Trigger 5
Enables or disables the A/D conversion start request
input from the MTU2S.
0: Disables the A/D conversion start by TRG4AN trigger
(MTU2S).
1: Enables the A/D conversion start by TRG4AN trigger
(MTU2S).
Start Trigger 4
Enables or disables the A/D conversion start request
input from the MTU2S.
0: Disables the A/D conversion start by TRG4BN trigger
(MTU2S).
1: Enables the A/D conversion start by TRG4BN trigger
(MTU2S).
Rev. 2.00 May. 08, 2008 Page 777 of 1200
REJ09B0344-0200